EC Designs

[a supprimer merci]

Voici les principes:

" there is a PLL master clock in this DAC, it is located inside the DIR9001 Toslink receiver. This chip already offers -very- low jitter (max. 50ps with the datasheet loop filter).

I modified its PLL loop filter so jitter stays even lower (even with very high jitter on the Toslink interface). It now acts as a flywheel, it can only -slowly- follow the input frequency changes, too slow to pass on jitter. The only disadvantage is that it takes longer to lock (approx. 1 second instead of milli seconds).

Crystal master clocks emit a powerful spectrum that reaches 10 meters and more, so it is very difficult to shield when its located inside the DAC right next to the D/A converters.

Low phase noise (jitter) crystal oscillators emit one huge peak signal at resonance (fundamental frequency), for example 11.2896 MHz, this is problematic. The master clock inside the DIR9001 is not very powerful (the complete chip draws only 25% of the power a single crystal master clock would typically consume) and has a spread spectrum that spreads this peak signal for reducing EMI peaking.

I only use low frequency clock signals from the DIR9001 (Highest equals 6.144 MHz at 96 KHz sample rate and only 2.8224 Mhz at 44 KHz sample rate). This is easier to handle compared to say a 48 or 96 MHz crystal oscillator plus high frequency audio clocks of 22.5792 and 24,576 MHz used in conventional USB DACs that produce a very powerful, highly complex summed noise spectrum.

I developed a new hardware decoder that exposes the DAC to the jitter spectrum (noise) for only 16 or 24 of the total 64 bits in a frame. This reduces the impact of jitter by 75% (when using 44.1) compared to I2S.

The novel Mosaic Mirror DAC is no longer sensitive to jitter like conventional DACs are. It consists of two identical but mirrored D/A converters that are merged together. One outputs a signal from +4V and down while the other outputs a signal from 0V up at the same time, hence the name mirror DAC. The signals meet at the centre (0V) where the signals and the noise on these signals fully cancel.

So I basically generate the output signal by varying the degree of signal cancellation. This way noise around the critical zero crossing area is lowest as both signals plus the common mode noise on it will cancel.

For clarity, jitter does change timing ever so slightly, this however is completely inaudible. Few pico seconds sample timing change is inaudible. The noise jitter dumps on the DAC output through demodulation is very audible, especially around the signal zero crossing area when jitter is no longer masked by louder signals.

The jitter riding on clock and data signals that reaches the DAC output will cause audible changes that are related to jitter. This is where I tackle jitter, I prevent this noise from reaching the DAC outputs by simply shutting these signals down completely for as long as possible.

I attached an oscillogram illustrating what I mean.

You see a 16 pulses (data & clock being injected into the DAC), followed by 16 bit silence (interface shut down completely). Then there is a small spike (sample is latched to the outputs) followed by 32 bit silence (interface completely shut down again).

I2S would switch all of the time (it never shuts down) so we get 100% jitter exposure (the jitter is IN the data and clock signals).

With the Mosaic Mirror DAC we only have 25% exposure as you can see on the oscillogram."



C'est également décrit sur le fil DIYAudio à partir d'ici: http://www.diyaudio.com/forums/digital-l...56357.html

Les commentaires suivants dans le fil sont intéressants. 

P.S. Ne pas me demander d'explications ! Je ne fais que rapporter...